Friday, October 30th
09:30 - 12:30
Chair: Masahiro Nakao
09:30 - 09:45
09:45 - 10:30
"OpenSHMEM: Introduction, Version 1.3, and Beyond"
Manjunath Gorentla Venkata
The OpenSHMEM is a predominant PGAS library interface specification.
It is a community effort to standardize the SHMEM programming models,
driven by Oak Ridge National Laboratory (ORNL), Department of Defense (DoD),
and University of Houston (UH). The community has released three versions
of the OpenSHMEM specification, and it will the latest version version 1.3
at SC15. In this talk, first, I will introduce OpenSHMEM, present
its history, and discuss the upcoming features. Then, I will discuss the
efforts preparing OpenSHMEM for the exascale era, and provide an overview
of the OpenSHMEM activities, which includes specification development,
reference implementation, and research. Lastly, I will provide an overview
of OpenSHMEM reference implementation and its network layer, UCX.
10:30 - 11:00
"Optimizing MPI Intra-node Communication with New Task Model for Many-core
Recently, number of cores in an HPC system node grows rapidly. Partitioned
Virtual Address Space(PVAS) is a new task model, which enables efficient
parallel processing in such many-core systems. The PVAS task model allows
multiple processes to run in the same address space, which means that
processes running on the PVAS task model can conduct intra-node
communication without overhead for crossing address space boundaries. In
this presentation, we show that PVAS task model can optimize MPI
intra-node communication performance. By using PVAS task model, message
can be copied from sender process's buffer to receiver process's buffer
directly. Moreover, PVAS task model enables MPI processes to access the
MPI objects of the other processes, which makes it possible to implement
efficient intra-node communication. We optimized the intra-node
communication of Open MPI, and the benchmark results show that the
optimized MPI intra-node communication improves MPI application
11:00 - 11:30
"MapReduce Frameworks on Multiple PVAS for Heterogeneous Computing Systems"
This study presents a MapReduce framework for building applications flexibly by the task model that exploits parallelism across host CPUs and Xeon Phi coprocessors. Heterogeneous computing system consisting of many-core and multi-core CPUs should tightly collaborate with the others in order to fully utilize the performance of CPUs. However, current MapReduce frameworks which are applied to many-core and multi-core CPUs are limited to execution on the shared-memory systems and some kind of communication method is needed to realize mutual collaboration between CPUs. In this study, the task execution model "Multiple Partitioned Virtual Address Space (M-PVAS)" is applied to the MapReduce framework to realize an application execution on the global virtual address space for the heterogeneous system. The M-PVAS implemented on Xeon and Xeon Phi system is possible to communicate between tasks on different CPUs with an overhead on a minimum of 2.0 usec. MapReduce framework is implemented on the M-PVAS system, and the effect of the MPVAS model is estimated by the MapReduce applications.
11:30 - 12:00
"Spare Node Substitution for Failure Nodes"
In the upcoming Exa-scale era, faults could happen more frequently than ever, and thus, many mechanisms to survive failures has been proposed and investigated. One of the mechanism is user-level fault mitigation to which user program handles failures in order that the program can survive from the failures and continue its execution. A simple method is that program continues its execution only with healthy nodes after failure. However, it is not suitable for some applications(e.g. stencil applications). Since a application must be executed with an unusual number of nodes after failure, it is difficult to load balance and keep the communication pattern. To deal with this problem, using spare nodes to substitute failed nodes is a solution. An important issue is how the failed nodes should be substituted with spare nodes. In this talk, we will show that the possibility of communication performance degradation due to the substitutions. Moreover, we will present and discuss several substitution methods.
12:00 - 12:30
"Throttling Approach Towards High Performance Collective MPI-IO"
Nowadays, MPI-IO is playing an important role for high performance
parallel I/O, especially collective MPI-IO is frequently used in
an underlying parallel I/O layer of HDF5 or PnetCDF.
Therefore performance improvement of collective MPI-IO leads to
performance improvement in HDF5 or PnetCDF.
A well-known MPI-IO implementation named ROMIO
has two-phase I/O optimization in such collective MPI-IO.
We have been focusing throttling approach named EARTH
(Effective Aggregation Rounds using THrottling)
for further performance improvements
of two-phase I/O on the K computer.
The EARTH optimization tunes the number of I/O requests
generated at the same time to reveal I/O contention
on a parallel file system and data aggregation on the K computer.
As a result, the EARTH optimization improves collective
MPI-IO performance up to twice the original I/O performance.
12:30 - 14:00
14:00 - 17:00
Chair: Atsushi Hori
14:00 - 14:45
"Designing Hybrid MPI+PGAS Library for Exascale Systems: MVAPICH2-X
Dhabaleswar K. Panda
This talk will focus on challenges in designing hybrid MPI+PGAS
library for exascale systems. Motivations, features and design
guidelines for supporting hybrid MPI and PGAS (OpenSHMEM, UPC and CAF)
programming model with the MVAPICH2-X library will be presented. The
role of unified communication runtime to support hybrid programming
models on InfiniBand, accelerators and co-processors will be outlined.
Unique capabilities of the hybrid MPI+PGAS model to re-design HPC
applications to harness performance and scalability will also be
presented through a set of case-studies.
14:45 - 15:30
"Towards Exascale with Global Arrays using Communication
Runtime at Extreme Scale (ComEx)"
Global Arrays is a Partitioned Global Address Space Programming
model, which uses Communication Runtime at Extreme Scale (ComEx) as its
communication backend for large scale systems. In this talk, Dr. Vishnu
will present the research conducted by the group on performance, and fault
tolerance aspects of Global Arrays and ComEx. He will present approaches
for designing ComEx on upcoming systems by using MPI as the backend ‹ by
using two-sided and one-sided semantics. A performance evaluation of this
design using NWChem and several other kernels shows the effectiveness of
this approach ‹ and similar performance in comparison to the native ports.
15:30 - 15:40
15:40 - 16:00
"Introduction of ACE (Advanced Communication library for Exa)
16:00 - 16:20
"Basic Layer and Data Library of ACP (Advanced Communication
16:20 - 16:40
"Simulation of RDMA Communication with NSIM-ACE"
16:40 - 17:00
"Development of Applications on ACP Library"
17:00 - 17:15